Semiconductor memory devices are typically classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are subdivided into dynamic random access memories (DRAMs) and static random access memories (SRAMs). Non-volatile memory types include mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs). Additionally, flash EEPROMs are advantageous as mass storage devices because their integration density is high compared with conventional EEPROMs.
Non-volatile semiconductor memories have attained broad utilization due to an ability to retain data within a device, even after power has been suspended. EEPROMs are non-volatile semiconductor memories that possess these abilities and additionally are able to store data by electrically erasing and writing storage devices. This programming process can be repeated over hundreds of thousands of cycles.
Due to the size and complexity of EEPROMs, some memory cell locations may be faulty. Faulty locations may be found during the manufacturing process and in particular, during a final test procedure. Faults are located to a bit column level. Additional memory cells, known as redundant memory locations, are fabricated to provide alternate bit columns. Faulty locations are replaceable by equivalent redundant bit columns within each memory plane. Faulty locations found in manufacturing are programmed into a content addressable memory (CAM) to be decoded as pointers to corresponding alternate locations. In parallel, the CAM and regular decode circuitry receive addresses being used for memory array access. When a faulty memory location address is received, a match to a CAM location is made and a redundant memory location pointer is produced. A memory array decoder uses the pointer to locate redundant bit columns. The redundant memory location is used in place of the faulty one to produce a correct memory output signal.
The content addressable memory is a central part of a redundant memory system. The CAM monitors requested addresses for memory access, compares requested addresses with addresses of predetermined faulty memory cell locations, and produces an alternate memory location pointer. Detection of the faulty memory address and production of the alternate memory pointer occur in time for the redundant location to be used by the rest of the memory system in a manner otherwise identical to the original location.
A memory segment address is latched in an address register during the period necessary for CAM circuitry to decode the column redundancy information pointer. Additionally, a register is utilized after decode of a redundant memory location pointer for a period that the information is required by the rest of the system. For a memory device with many tens or hundreds of segments, multiple sets of addresses and column redundancy information registers are called for in conventional design practices. Multiple sets of registers mean a significant amount of area in the device substrate is dedicated to duplicating the registers at significant cost for fabrication and die area. Good economics would point to avoidance of extensive use of device area in supporting multiple sets of address and redundant column information registers if an alternative might be found. It would be desirable to determine a way of utilizing a single set of registers to provide address and redundant column information storage and be able to support concurrent read and write operations in a memory system.